In a typical VLSI system, there are millions of electrical signals. They are used to make the system perform what it is designed to do. Among those, the most important one is the clock signal. From an operational perspective, clock is the timekeeper of the electrical world inside the chip. From a structural perspective, clock generator is the heart of the chip; clock signal is the blood; and clock distribution network is the vessel.
The purpose of a VLSI system is for processing information. The efficiency of performing this task is highly dependent on its internal time scale. This time scale is defined by the clock signal. There are two major concerns when a clock signal is created and used: the clock frequency and the frequency resolution. In addition, another issue is also important: the speed that the time scale can be switched from one to another (the speed of clock frequency switching). The task of creating such clock signal for driving electronic system is often termed frequency synthesis.
In the field of frequency synthesis, there are three major technologies developed during the evolution of several decades: analog direct frequency synthesis, Digital Direct Synthesis (DDS) and PLL based indirect frequency synthesis. Each of them has been used effectively in its appropriate application domains. For on-chip frequency generation, PLL has been the designers' first choice due to its easy integration with other circuitries on chip. Regardless the tremendous effort spent on the study of frequency synthesis, however, there are still two problems that have not been solved to our complete satisfaction: arbitrary frequency generation (small frequency granularity or fine frequency resolution) and instantaneous frequency switching (fast frequency switching speed). In contrast, when analog voltage is concerned, designer can reach almost any voltage level (within a given range and a given quantization error) and, further, voltage level can be switched from one to another within a short period of time (given reasonable loading).
To address the issue of small frequency granularity, a novel concept, Time-Average-Frequency (TAF), is proposed in 2008 [1]. It removes the constraint that all the cycles in a clock pulse train have to be equal in their length-in-times. As a result, a TAF clock signal can be created by using two, or more, types of cycles. Small frequency granularity can be obtained by adjusting the weighing factor in very fine step. Fast frequency switching is accomplished through directly synthesizing the length of each individual clock pulse. Together, a new technology, Time-Average-Frequency Direct Period Synthesis, is emerged [2]. Its aim is to provide the features of arbitrary frequency generation and instantaneous frequency switching to chip designers and system users. The clock signal bearing the features of arbitrary frequency generation and instantaneous frequency switching is termed flexible clock signal. The impact, its influence on the design of various electronic systems, is extensively discussed in [2] as well.
A programmable logic device is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a programmable logic device has an undefined function at the time of manufacture. Before the programmable logic device can be used in a circuit, it must be programmed (or configured). Field programmability is achieved through switches, which are transistors controlled by memory elements or fuses. The switches control the following two aspects of the programmable logic device: the interconnection among wire segments, the configuration of logic blocks. The technology of programmable element varies from vendor to vendor and it can be classified into three categories: SRAM based, fuse based and EPROM/EEPROM/Flash based. Although different in operation, they all share the common property: configure the switch in one of the ‘ON’ and ‘OFF’ positions.
Among commercially available programmable logic chips, the architectures differ from vendor to vendor. They can be characterized by two factors: 1) the structure and content of logic block, 2) the structure and content of routing resource. Nowadays, there are two major technologies in the family of programmable logic chips: FPGA and CPLD. These two types of devices have very different internal architectures. FPGA is considered as ‘fine-grain’ because it contains a lot of tiny logic blocks which have flip-flop, combination logic, and memory. It is designed for complex applications. The time delay in FPGA is unpredictable because of its architecture. FPGA's architecture allows the chip to have a very high logic capacity. It is used in designs that require a high gate count. It is a type of a programmable logic chip that can be programmed to do almost any kind of digital function. CPLD is considered as ‘coarse-grain’ type of devices. Compared to FPGA, it contains only a few but larger blocks of logic. It offers a much faster operation speed because of its simpler, ‘coarse grain’ architecture. Additionally, the programming in CPLD is carried out using fuse, EPROM or EEPROM as contrast to the use of SRAM in FPGA programming. Thus, it is non-volatile. Since it has a less complex architecture, the delay is much predictable in CPLD. CPLD is often used for simple logic applications. It is more suitable for small gate count designs.
The important features of arbitrary frequency generation and instantaneous frequency switching enabled by TAF-DPS clock generator are extremely useful for future electronic system designs. They are the enabler for future innovations. Meanwhile, the field programmability offered from programmable logic device is an ideal platform for exploring new ideas. Therefore, implementing TAF-DPS on programmable logic device can provide people with another dimension for innovation. It is the engine for a suite of new applications in electronic system design.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.